Institute of Fundamental Technological Research
Polish Academy of Sciences


Damian Cacko, MSc

Department of Experimental Mechanics (ZMD)
PhD student
telephone: (+48) 22 826 12 81 ext.: 248
room: 537

Conference papers
1.  Ranachowski Z., Schabowicz K., Gorzelańczyk T., Lewandowski M., Cacko D., Katz T., Dębowski T., Investigation of Acoustic Properties of Fibre-Cement Boards, IEEE 2018, IEEE Joint Conference - Acoustics, 2018-09-11/09-14, Ustka (PL), DOI: 10.1109/ACOUSTICS.2018.8502341, pp.275-279, 2018

The paper describes two different techniques of ultrasound measurements performed in fibre cement boards, the material widely applied in building technology. An in-house device dedicated for fibre-cement board testing is also presented. To overcome the difficulty of determining the arrival time of the waveform of a longitudinal wave travelling across a thin and inhomogeneous body, a cross-correlation method of signal processing was proposed and applied

ultrasound, fibre-cement board, waveform cross correlation coefficient

Ranachowski Z. - IPPT PAN
Schabowicz K. - Wroclaw University of Science and Technology (PL)
Gorzelańczyk T. - Wroclaw University of Science and Technology (PL)
Lewandowski M. - IPPT PAN
Cacko D. - IPPT PAN
Katz T. - IPPT PAN
Dębowski T. - IPPT PAN
2.  Cacko D., Walczak M., Lewandowski M., Low-Power Ultrasound Imaging on Mixed FPGA/GPU Systems, IEEE 2018, IEEE Joint Conference - Acoustics, 2018-09-11/09-14, Ustka (PL), DOI: 10.1109/ACOUSTICS.2018.8502371, pp.42-47, 2018

Portable and hand-held ultrasound imagers have the potential to revolutionize Point-of-Care medical diagnostics. There is great need for low-cost, portable scanners with extended battery life. In this paper, we focus on hardware-software partitioning in heterogeneous systems where both field-programmable gate array (FPGA) and graphics processing unit (GPU) resources are available. We present the architecture of a prototype test scanner for the evaluation of various hardware-software partitioning strategies. The system is equipped with the Intel Arria 10 FPGA and the Nvidia Tegra X2 mobile GPU. FPGA-based beamformers: Delay-and-Sum and Filtered Multiply-and-Sum, were implemented. These 32-channel beamformer blocks are integrated into a complete dataflow along with the data acquisition, RF filter, quadrature demodulator, and envelope detector. The designed dataflow allows one to allocate processing functions to either hardware (FPGA) or software (GPU) to explore various imaging scenarios and optimize power consumption. A dedicated measurement setup facilitates measuring power consumption of both FPGA and GPU. The developed setup will provide a reliable experimental system power characterization.

ultrasound imaging, ultrasound scanner, point-ofcare ultrasound, beamforming, low-power, FPGA, GPU processing

Cacko D. - IPPT PAN
Walczak M. - IPPT PAN
Lewandowski M. - IPPT PAN

Category A Plus


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